1. Technical Field
Embodiments of the present invention are related to the field of electronic devices, and in particular, to operation resiliency to errors in electronic devices.
2. Description of Related Art
Single event upsets (SEUs), also referred to as soft errors (SERs), are radiation-induced transient errors in digital systems caused by high energy particles such as neutrons generated from cosmic rays and alpha particles from packaging material. For designs manufactured at advanced technology nodes (130 nm, 90 nm, and so on), SEUs are gaining in importance. Hence, soft errors may be significant for microprocessors, network processors, high end routers and network storage components that target enterprise and applications with very high reliability, data integrity and availability. More specifically, bistables (latches and flip-flops) may be major contributors to the system-level soft error rate.
One of the problems presented by the increased complexity of modern very large scale integrated (VLSI) chips is the difficulty in debugging them and qualifying them for full production. A scanout mechanism helps designers to observe important internal states of internal nodes in the chip in a non-intrusive manner during normal operation (in real time). The scanout mechanism includes the ability to capture the observed signals and to serially shift them out so as to simplify the isolation of circuit, speed, logic and microcode bugs. Scanout implementations in major high-end microprocessors involve significant circuitry and clock signals that are used only during post-silicon debug and production testing. These resources generally are not used during normal system operation, although they occupy additional area and draw additional leakage power.
Referring to FIG. 1, a system/scanout cell 10 may have a scanout circuit 12 and a system circuit 14. To implement a scanout function in a chip, such as a processor chip, one or more shift registers (often referred to as scanout chains) are arranged in the chip by serially connecting a plurality of scanout circuits 12 (only one cell shown) so as to observe key internal states at various internal test nodes. Such internal nodes frequently are chosen for their strategic importance in the chip's operation (hence important for debug). Both the scanout and system circuits 12 and 14 are coupled to receive the same data from one of the internal test nodes. This data may be generated by an upstream combinational logic circuit (not shown). The scanout circuit 12 includes a first latch LA and a second latch LB configured in a master/slave relationship and the system circuit 14 includes a first latch PH2 and a second latch PH1 configured in a master/slave relationship. The scanout circuit 12 further includes an Exclusive OR (XOR) gate 16 having inputs from two AND gates 18 and 20, with the AND gate 18 having as inputs a signal SHIFT and a shifted data input signal SDI and AND gate 20 having as inputs a signal LOAD and a data signal D. Referring a truth table in FIG. 2, the system/scanout cell 10 typically has two scanout modes of operation: “snapshot” and “signature” modes, with the two modes being determined by the states of the signals LOAD and SHIFT.